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FEATURES
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LTC2216/LTC2215 16-Bit, 80Msps/65Msps Low Noise ADC DESCRIPTION
The LTC(R)2216/LTC2215 are 80Msps/65Msps sampling 16bit A/D converters designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 400MHz. The input range of the ADC is fixed at 2.75VP-P. The LTC2216/LTC2215 are perfect for demanding communications applications, with AC performance that includes 81.5dBFS noise floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 85fsRMS allows undersampling of high input frequencies while maintaining excellent noise performance. Maximum DC specs include 3.5LSB INL, 1LSB DNL (no missing codes). The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC- inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Sample Rate: 80Msps/65Msps 81.5dBFS Noise Floor 100dB SFDR SFDR >95dB at 70MHz 85fsRMS Jitter 2.75VP-P Input Range 400MHz Full Power Bandwidth S/H Optional Internal Dither Optional Data Output Randomizer LVDS or CMOS Outputs Single 3.3V Supply Power Dissipation: 970mW/700mW Clock Duty Cycle Stabilizer Pin-Compatible with LTC2208, LTC2217 64-Pin (9mm x 9mm) QFN Package
APPLICATIONS
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Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems ATE
TYPICAL APPLICATION
3.3V SENSE VCM 2.2F 1.575V COMMON MODE BIAS VOLTAGE INTERNAL ADC REFERENCE GENERATOR OVDD 0.5V TO 3.6V 1F OF CLKOUT D15 * * * D0 OGND CLOCK/DUTY CYCLE CONTROL VDD GND ENC
+
LTC2216: 64k Point FFT, fIN = 4.9MHz, -1dBFS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
0 10 20 30 FREQUENCY (MHz) 40
22165 TA01b
ANALOG INPUT AIN-
S/H AMP
-
16-BIT PIPELINED ADC CORE
CORRECTION LOGIC AND SHIFT REGISTER
OUTPUT DRIVERS
CMOS OR LVDS
3.3V 1F 1F 1F
22165 TA01
ENC
-
SHDN
DITH
MODE
LVDS
RAND
ADC CONTROL INPUTS
AMPLITUDE (dBFS)
AIN+
+
22165f
1
LTC2216/LTC2215 ABSOLUTE MAXIMUM RATINGS
OVDD = VDD (Notes 1 and 2)
PIN CONFIGURATION
TOP VIEW 64 NC 63 RAND 62 MODE 61 LVDS 60 OF+/OFA 59 OF-/DA15 58 D15+/DA14 57 D15-/DA13 56 D14+/DA12 55 D14-/DA11 54 D13+/DA10 53 D13-/DA9 52 D12+/DA8 51 D12-/DA7 50 OGND 49 OVDD SENSE 1 GND 2 VCM 3 GND 4 VDD 5 VDD 6 GND 7 AIN+ 8 AIN- 9 GND 10 GND 11 ENC+ 12 ENC- 13 GND 14 VDD 15 VDD 16 65 48 D11+/DA6 47 D11-/DA5 46 D10+/DA4 45 D10-/DA3 44 D9+/DA2 43 D9-/DA1 42 D8+/DA0 41 D8-/CLKOUTA 40 CLKOUT+/CLKOUTB 39 CLKOUT -/OFB 38 D7+/DB15 37 D7-/DB14 36 D6+/DB13 35 D6-/DB12 34 D5+/DB11 33 D5-/DB10
Supply Voltage (VDD) ................................... -0.3V to 4V Digital Output Supply Voltage (OVDD) .......... -0.3V to 4V Digital Output Ground Voltage (OGND)........ -0.3V to 1V Analog Input Voltage (Note 3) ..... -0.3V to (VDD + 0.3V) Digital Input Voltage .................... -0.3V to (VDD + 0.3V) Digital Output Voltage ................-0.3V to (OVDD + 0.3V) Power Dissipation.............................................2000mW Operating Temperature Range LTC2215C/LTC2216C ............................... 0C to 70C LTC2215I/LTC2216I..............................-40C to 85C Storage Temperature Range ..................-65C to 150C
TJMAX = 150C, JA = 20C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC2215CUP#PBF LTC2215IUP#PBF LTC2216CUP#PBF LTC2216IUP#PBF LEAD BASED FINISH LTC2215CUP LTC2215IUP LTC2216CUP LTC2216IUP TAPE AND REEL LTC2215CUP#TRPBF LTC2215IUP#TRPBF LTC2216CUP#TRPBF LTC2216IUP#TRPBF TAPE AND REEL LTC2215CUP#TR LTC2215IUP#TR LTC2216CUP#TR LTC2216IUP#TR PART MARKING LTC2215UP LTC2215UP LTC2216UP LTC2216UP PART MARKING LTC2215UP LTC2215UP LTC2216UP LTC2216UP PACKAGE DESCRIPTION 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN PACKAGE DESCRIPTION 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
VDD 17 GND 18 SHDN 19 DITH 20 -/DB0 21 D0 +/DB1 22 DO D1-/DB2 23 D1+/DB3 24 D2-/DB4 25 D2+/DB5 26 D3-/DB6 27 D3+/DB7 28 D4-/DB8 29 D4+/DB9 30 OGND 31 OVDD 32
22165f
2
LTC2216/LTC2215
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER Integral Linearity Error Differential Linearity Error Offset Error Offset Drift Gain Error Full-Scale Drift Transition Noise External Reference Internal Reference External Reference External Reference
l
CONVERTER CHARACTERISTICS
CONDITIONS
MIN
l l l
TYP 1.2 0.16/-0.2 1.5 4 0.3 -65 12 2
MAX 3.5 1 8 1
UNITS LSB LSB mV V/C %FS
ppm/C ppm/C
Differential Analog Input (Note 5) Differential Analog Input (Note 6)
LSBRMS
ANALOG INPUT
SYMBOL VIN VIN, CM IIN ISENSE IMODE ILVDS CIN tAP tJITTER CMRR BW-3dB PARAMETER
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS 3.135V VDD 3.465V Differential Input (Note 7) 0V AIN+, AIN- VDD 0V SENSE VDD
l l l
MIN 1.2 -1 -3
TYP 2.75 1.575
MAX 1.8 1 3
UNITS VP-P V A A A A pF pF ns fs RMS dB MHz
Analog Input Range (AIN+ - AIN-) Analog Input Common Mode Analog Input Leakage Current SENSE Input Leakage Current MODE Pin Pull-Down Current to GND LVDS Pin Pull-Down Current to GND Analog Input Capacitance Sample-and-Hold Acquisition Delay Time Sample-and-Hold Aperture Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth
10 10 Sample Mode ENC+ < ENC- Hold Mode ENC+ > ENC- 9.1 1.8 0.35 85 1.2V < (AIN+ = AIN-) <1.8V RS < 25 80 400
22165f
3
LTC2216/LTC2215 DYNAMIC ACCURACY
SYMBOL PARAMETER SNR Signal-to-Noise Ratio
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS with 2.75V range unless otherwise noted. (Note 4)
LTC2215 CONDITIONS 5MHz Input 15MHz Input, TA = 25C 15MHz Input 30MHz Input, TA = 25C 70MHz Input, TA = 25C 70MHz Input 140MHz Input
l l
LTC2216 MAX MIN 80.6 80.2 80 79.7 TYP 81.3 81.2 80.8 81.1 80.5 80.2 79 100 88 88 85 84 100 99 95 97 97 91 105 94 93 105 105 103 100 81.3 80.2 80 79.6 79.4 81.1 80.7 80.8 80.4 80.1 78.8 105 105 105 105 100 115 100 115 115 115 110 100 97 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc
MIN 80.8 80.5 80 79.7
TYP 81.5 81.4 81 81.2 80.6 80.2 79 100
SFDR
Spurious Free Dynamic Range 2nd or 3rd Harmonic
5MHz Input 15MHz Input, TA = 25C 15MHz Input 30MHz Input 70MHz Input, TA = 25C 70MHz Input 140MHz Input
l l
88 88 85 84
100 96 91 96 95 89 105
SFDR
Spurious Free Dynamic Range 4th Harmonic or Higher
5MHz Input 15MHz Input 30MHz Input 70MHz Input 140MHz Input
l l
95 94
105 105 104 100 81.5
S/(N+D) Signal-to-Noise Plus Distortion Ratio
5MHz Input 15MHz Input, TA = 25C 15MHz Input 30MHz Input 70MHz Input, TA = 25C 70MHz Input 140MHz Input
l l
80.3 80.2 79.3 79.2
81.2 80.8 80.9 80.3 80 78.8 105 105 105 105 100 115
SFDR
Spurious Free Dynamic Range at -25dBFS Dither "OFF"
5MHz Input 15MHz Input 30MHz Input 70MHz Input 140MHz Input
SFDR
Spurious Free Dynamic Range at -25dBFS Dither "ON"
5MHz Input 15MHz Input 30MHz Input 70MHz Input 140MHz Input
l
100
115 115 115 110 100 96
IMD
Intermodulation Distortion
fIN1 = 14MHz, fIN2 = 21MHz, -7dBFS fIN1 = 67MHz, fIN2 = 74MHz, -7dBFS
22165f
4
LTC2216/LTC2215
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0 IOUT = 0 3.135V VDD 3.465V | IOUT | 0.8mA
l
COMMON MODE BIAS CHARACTERISTICS
MIN 1.475
TYP 1.575 60 2.4 1.1
MAX 1.675
UNITS V
ppm/C
mV/ V
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL VID VICM RIN CIN Logic Inputs VIH VIL IIN CIN OVDD = 3.3V VOH VOL ISOURCE ISINK OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL STANDARD LVDS VOD VOS Low Power LVDS VOD VOS Differential Output Voltage Output Common Mode Voltage 100 Differential Load 100 Differential Load Differential Output Voltage Output Common Mode Voltage 100 Differential Load 100 Differential Load High Level Output Voltage Low Level Output Voltage VDD = 3.3V VDD = 3.3V High Level Output Voltage Low Level Output Voltage VDD = 3.3V VDD = 3.3V High Level Output Voltage Low Level Output Voltage Output Source Current Output Sink Current VDD = 3.3V VDD = 3.3V VOUT = 0V VOUT = 3.3V High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7) PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance CONDITIONS (Note 7) Internally Set Externally Set (Note 7) (See Figure 2) (Note 7) Encode Inputs (ENC+, ENC-)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
MIN
l
TYP
MAX
UNITS V
0.2 1.6 1.2 6 3 3
V V k pF V
l l l
2 0.8 10 1.5
V A pF
LOGIC OUTPUTS (CMOS MODE) IO = -10A IO = -200A IO = 160A IO = 1.6mA 3.299 3.29 0.01 0.10 -50 50 IO = -200A IO = 1.60mA IO = -200A IO = 1.60mA 2.49 0.1 1.79 0.1 0.4 V V V V mA mA V V V V
l l
3.1
LOGIC OUTPUTS (LVDS MODE)
l l l l
247 1.125 125 1.125
350 1.2 175 1.2
454 1.375 250 1.375
mV V mV V
22165f
5
LTC2216/LTC2215 POWER REQUIREMENTS
SYMBOL PARAMETER VDD PSHDN OVDD IVDD IOVDD PDIS OVDD IVDD IOVDD PDIS OVDD IVDD PDIS Analog Supply Voltage Shutdown Power Output Supply Voltage Analog Supply Current Output Supply Current Power Dissipation Output Supply Voltage Analog Supply Current Output Supply Current Power Dissipation Output Supply Voltage Analog Supply Current Power Dissipation (Note 8) (Note 8)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS unless otherwise noted. (Note 4)
LTC2215 CONDITIONS (Note 8) SHDN = VDD (Note 8)
l l l l l l l l l l l l
LTC2216 MAX MIN TYP 3.3 17 3.6 290 90 1254 3.6 290 50 1122 3.6 0.5 295 970 3 3 3.3 300 75 1240 3.3 298 42 1120 3.6 370 90 1518 3.6 370 50 1386 3.6 370 1220 MAX 3.465 UNITS V mW V mA mA mW V mA mA mW V mA mW 3.465 3.135
MIN 3.135
TYP 3.3 17
Standard LVDS Output Mode 3 3.3 217 75 964 3 3.3 215 42 848 0.5 212 700
Low Power LVDS Output Mode
CMOS Output Mode 290 957
TIMING CHARACTERISTICS
SYMBOL fS tL tH PARAMETER Sampling Frequency ENC Low Time ENC High Time
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
LTC2215 CONDITIONS (Note 8) Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) (Note 7) (Note 7) (tC-tD) (Note 7)
l l l l l
LTC2216 MAX 65 500 500 500 500 3.8 3.8 0.6 MIN 1 5.94 4.06 5.94 4.06 1.3 1.3 -0.6 6.25 6.25 6.25 6.25 2.5 2.5 0 0.5 0.5 7 4 4 0.6 1.3 1.3 -0.6 2.7 2.7 0 7 7 4 4 0.6 TYP MAX 80 500 500 500 500 3.8 3.8 0.6 UNITS MHz ns ns ns ns ns ns ns ns ns Cycles ns ns ns Cycles Cycles
MIN 1 7.31 5 7.31 5 1.3 1.3 -0.6
TYP 7.692 7.692 7.692 7.692 2.5 2.5 0 0.5 0.5 7
LVDS Output Mode (Standard and Low Power) tD tC tSKEW tRISE tFALL ENC to DATA Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Output Rise Time Output Fall Time
l l l
Data Latency Data Latency CMOS Output Mode tD tC tSKEW ENC to DATA Delay ENC to CLKOUT Delay DATA to CLKOUT Skew (Note 7) (Note 7) (tC-tD) (Note 7) Full Rate CMOS Demuxed
l l l
1.3 1.3 -0.6
2.7 2.7 0 7 7
Data Latency Data Latency
22165f
6
LTC2216/LTC2215 ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND, with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 65MHz (LTC2215) or 80MHz (LTC2216), LVDS outputs, differential ENC+/ENC- = 2VP-P sine wave with 1.6V common mode, input range = 2.75VP-P with differential drive, unless otherwise specified. Note 5: Integral nonlinearity is defined as the deviation of a code from a "best fit straight line" to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from -1/2LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2's complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions.
TIMING DIAGRAM
LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels
tAP ANALOG INPUT
N+1 N+2 N+3
N+4
N tH tL
ENC
-
ENC+ tD D0-D15, OF tC N-7 N-6 N-5 N-4 N-3
CLKOUT+ CLKOUT -
22165 TD01
22165f
7
LTC2216/LTC2215 TIMING DIAGRAMS
Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels
tAP ANALOG INPUT N+1 N+2 tH tL ENC
-
N+4 N+3
N
ENC+ tD DA0-DA15, OFA tC CLKOUTA CLKOUTB N-7 N-6 N-5 N-4 N-3
DB0-DB15, OFB
HIGH IMPEDANCE
22165 TD02
Demultiplexed CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels
tAP ANALOG INPUT N+1 N+2 tH tL ENC- ENC+ tD DA0-DA15, OFA tD DB0-DB15, OFB tC CLKOUTA CLKOUTB
22165 TD03
N+4 N+3
N
N-8
N-6
N-4
N-7
N-5
N-3
22165f
8
LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2216 Integral Nonlinearity (INL) vs Output Code, Dither "Off"
2.0 1.5 1.0 2.0 1.5 1.0
LTC2216 Integral Nonlinearity (INL) vs Output Code, Dither "On"
1.0 0.8 0.6 0.4 DNL ERROR (LSB)
LTC2216 Differential Nonlinearity (DNL) vs Output Code
INL ERROR (LSB)
INL ERROR (LSB)
0.5 0.0 -0.5 -1.0 -1.5 -2.0
0.5 0.0 -0.5 -1.0 -1.5 -2.0
0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0
0
16384 32768 OUTPUT CODE
49152
65536
22165 G01
0
16384 32768 OUTPUT CODE
49152
65536
22165 G02
0
16384 32768 OUTPUT CODE
49152
65536
22165 G03
LTC2216 AC Grounded Input Histogram
14000 12000 10000
LTC2216 64k Point FFT, fIN = 4.9MHz, -1dBFS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
0 10 20 30 FREQUENCY (MHz) 40
22165 G05
LTC2216 64k Point FFT, fIN = 15.1MHz, -1dBFS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
0 10 20 30 FREQUENCY (MHz) 40
22165 G06
AMPLITUDE (dBFS)
COUNT
8000 6000 4000 2000 0 32762
32771
OUTPUT CODE
32780
22165 G04
LTC2216 64k Point FFT, fIN = 15.1MHz, -20dBFS, Dither "Off"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
0 10 20 30 FREQUENCY (MHz) 40
22165 G07
LTC2216 64k Point FFT, fIN = 15.1MHz, -20dBFS, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
0 10 20 30 FREQUENCY (MHz) 40
22165 G08
AMPLITUDE (dBFS)
LTC2216 64k Point 2-Tone FFT, fIN = 14.25MHz and 21.5MHz, -7dBFS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
0 10 20 30 FREQUENCY (MHz) 40
22165 G09
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
22165f
9
LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2216 64k Point 2-Tone FFT, fIN = 14.25MHz and 21.5MHz, -25dBFS, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 30 FREQUENCY (MHz) 40
22165 G10
LTC2216 SFDR vs Input Level, fIN = 15.2MHz, Dither "Off"
140 130 120 110 SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 0 20 30 10 INPUT LEVEL (dBFS) 40
22165 G11
LTC2216 SFDR vs Input Level, fIN = 15.2MHz, Dither "On"
140 130 120 110 SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 0
AMPLITUDE (dBFS)
22165 G12
LTC2216 SNR vs Input Level, fIN = 15.2MHz
82 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2216 64k Point FFT, fIN = 28.7MHz, -1dBFS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2216 64k Point FFT, fIN = 70.2MHz, -1dBFS
81 SNR (dBFS)
AMPLITUDE (dBFS)
80
79
78 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
0
10
20 FREQUENCY (MHz)
30
40
22165 G14
AMPLITUDE (dBFS)
0
10
20 FREQUENCY (MHz)
30
40
22165 G15
22165 G13
LTC2216 64k Point FFT, fIN = 70.1MHz, -20dBFS, Dither "Off"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2216 64k Point FFT, fIN = 70.1MHz, -20dBFS, Dither "On"
140 130 120 110 SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 0 10 20 FREQUENCY (MHz) 30 40
22165 G17
LTC2216 SFDR vs Input Level, fIN = 70.5MHz, Dither "Off"
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
10
20 FREQUENCY (MHz)
30
40
22165 G16
30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
22165 G18
22165f
10
LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2216 SFDR vs Input Level, fIN = 70.5MHz, Dither "On"
140 130 120 SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 0
78 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) SNR (dBFS) 80 82
LTC2216 SNR vs Input Level, fIN = 70.5MHz
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2216 64k Point 2-Tone FFT, fIN = 67.2MHz and 74.4MHz, -7dBFS
79
AMPLITUDE (dBFS)
110
81
0
0
10
20 FREQUENCY (MHz)
30
40
22165 G21
22165 G19
22165 G20
LTC2216 64k Point 2-Tone FFT, fIN = 67.2MHz and 74.4MHz, -25dBFS, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 FREQUENCY (MHz) 30 40
22165 G22
LTC2216 64k Point FFT, fIN = 140.5MHz, -1dBFS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 FREQUENCY (MHz) 30 40
22165 G23
LTC2216 64k Point FFT, fIN = 140.1MHz, -20dBFS, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 30 FREQUENCY (MHz) 40
22165 G24
AMPLITUDE (dBFS)
LTC2216 SFDR vs Input Level, fIN = 140.5MHz, Dither "Off"
140 130 120 110 SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 0 140 130 120 110 100 90 80 70 60 50 40
AMPLITUDE (dBFS)
LTC2216 SFDR vs Input Level, fIN = 140.5MHz, Dither "On"
82
AMPLITUDE (dBFS) SNR (dBFS)
LTC2216 SNR vs Input Level, fIN = 140.5MHz
81
80
79
30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
78 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
22165 G25
22165 G26
22165 G27
22165f
11
LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2216 SFDR (HD2 and HD3) vs Input Frequency
110 105 100 SNR (dBFS)
SFDR (dBc)
LTC2216 SNR vs Input Frequency
82 110 81
SNR (dBFS) AND SFDR (dBc)
LTC2216 SNR and SFDR vs Sample Rate, fIN = 5.2MHz
LIMIT 105 100 95 90 85 SNR 80 75 70 SFDR
HD2
95 90 85 80 75 70 0
80 HD3 79 78 77 76 50 100 150 200 INPUT FREQUENCY (MHz) 250
22165 G28
SFDR
0
50 100 150 200 INPUT FREQUENCY (MHz)
250
22165 G29
0
40 80 SAMPLE RATE (Msps)
120
22165 G30
LTC2216 SNR and SFDR vs Supply Voltage (VDD), fIN = 5.1MHz
110 LOWER LIMIT 105 375
LTC2216 IVDD vs Sample Rate and Supply Voltage, fIN = 5MHz, -1dBFS
VDD = 3.465V
SNR (dBFS) AND SFDR (dBc)
100 95 SFDR 90 85 SNR 80 75 70 2.8 225 IVDD (mA) UPPER LIMIT 325 VDD = 3.135V 275 VDD = 3.3V
3.0 3.2 3.4 SUPPLY VOLTAGE (V)
3.6
22165 G31
0
40 80 120 SAMPLE RATE (Msps)
160
22165 G32
LTC2216 SNR and SFDR vs Clock Duty Cycle, fIN = 5.2MHz
110 SFDR DCS ON SFDR DCS OFF SFDR (dBc) 90 SNR DCS OFF 80 SNR DCS ON 70 110 105 100 SNR (dBFS) AND SFDR (dBc) 100 95 90 85 80 75 70 65 60 30 40 50 60 DUTY CYCLE (%) 70
22165 G33
LTC2216 SFDR vs Analog Input Common Mode Voltage, 5MHz and 70MHz, -1dBFS
5MHz
70MHz
60 0.5 0.75 1 1.25 1.5 1.75 2 ANALOG INPUT COMMON MODE VOLTAGE (V)
22165 G34
22165f
12
LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2215 Integral Nonlinearity (INL) vs Output Code, Dither "Off"
2.0 1.5 1.0 2.0 1.5 1.0
LTC2215 Integral Nonlinearity (INL) vs Output Code, Dither "On"
1.0 0.8 0.6 0.4
LTC2215 Differential Nonlinearity (DNL) vs Output Code
INL ERROR (LSB)
INL ERROR (LSB)
DNL ERROR (LSB) 0 16384 32768 OUTPUT CODE 49152 65536
22165 G43
0.5 0.0 -0.5 -1.0 -1.5 -2.0
0.5 0.0 -0.5 -1.0 -1.5
0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 OUTPUT CODE 49152 65536
22165 G44
0
16384 32768 OUTPUT CODE
49152
65536
22165 G42
-2.0
LTC2215 AC Grounded Input Histogram
14000 12000 AMPLITUDE (dBFS) 10000 COUNT 8000 6000 4000 2000 0 3275 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2215 64k Point FFT, fIN = 4.9MHz, -1dBFS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2215 64k Point FFT, fIN = 15.1MHz, -1dBFS
32768 OUTPUT CODE
32777
22165 G45
0
10 20 FREQUENCY (MHz)
30
22165 G46
AMPLITUDE (dBFS)
0
10 20 FREQUENCY (MHz)
30
22165 G47
LTC2215 64k Point FFT, fIN = 15.1MHz, -20dBFS, Dither "Off"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 FREQUENCY (MHz) 30
22165 G48
LTC221564k Point FFT, fIN = 15.1MHz, -20dBFS, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 FREQUENCY (MHz) 30
22165 G49
LTC2215 64k Point 2-Tone FFT, fIN = 14.25MHz and 21.5MHz, -7dBFS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 FREQUENCY (MHz) 30
22165 G50
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
22165f
13
LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2215 64k Point 2-Tone FFT, fIN = 14.25MHz and 21.5MHz, -25dBFS, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 FREQUENCY (MHz) 30
22165 G51
LTC2215 SFDR vs Input Level, fIN = 15.2MHz, Dither "Off"
140 130 120 110 SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 140 130 120 110 100 90 80 70 60 50 40
LTC2215 SFDR vs Input Level, fIN = 15.2MHz, Dither "On"
AMPLITUDE (dBFS)
0
30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
22165 G52
22165 G53
LTC2215 SNR vs Input Level, fIN = 15.2MHz
82 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2215 64k Point FFT, fIN = 28.7MHz, -1dBFS
80
79
78 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
81 SNR (dBFS)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2215 64k Point FFT, fIN = 70.2MHz, -1dBFS
0
0
10 20 FREQUENCY (MHz)
30
22165 G55
0
10
20
30
22165 G56
FREQUENCY (MHz)
22165 G54
LTC2215 64k Point FFT, fIN = 70.1MHz, -20dBFS, Dither "Off"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 FREQUENCY (MHz) 30
22165 G57
LTC221564k Point FFT, fIN = 70.1MHz, -20dBFS, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 FREQUENCY (MHz) 30
22165 G58
LTC2215 SFDR vs Input Level, fIN = 70.5MHz, Dither "Off"
140 130 120 110 SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
22165 G59
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LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2215 SFDR vs Input Level, fIN = 70.5MHz, Dither "On"
140 130 120 SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
78 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) SNR (dBFS) 80 82
LTC2215 SNR vs Input Level, fIN = 70.5MHz
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
LTC2215 64k Point 2-Tone FFT, fIN = 67.2MHz and 74.4MHz, -7dBFS
79
AMPLITUDE (dBFS)
110
81
0
0
10 20 FREQUENCY (MHz)
30
22165 G62
22165 G60
22165 G61
LTC2215 64k Point 2-Tone FFT, fIN = 67.2MHz and 74.4MHz, -25dBFS, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 FREQUENCY (MHz) 30
22165 G63
LTC2215 64k Point FFT, fIN = 140.5MHz, -1dBFS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 FREQUENCY (MHz) 30
22165 G64
LTC221564k Point FFT, fIN = 140.1MHz, -20dBFS, Dither "On"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 FREQUENCY (MHz) 30
22165 G65
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2215 SFDR vs Input Level, fIN = 140.5MHz, Dither "Off"
140 130 120 110 SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
LTC2215 SFDR vs Input Level, fIN = 140.5MHz, Dither "On"
140 130 120 110 100 90 80 70 60 50 40 30 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
LTC2215 SNR vs Input Level, fIN = 140.5MHz
82
81 SNR (dBFS)
80
79
22165 G66
22165 G67
78 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
22165 G68
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LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2215 SFDR (HD2 and HD3) vs Input Frequency
110 105 100
SFDR (dBc)
LTC2215 SNR vs Input Frequency
82 81 80
SNR (dBFS) AND SFDR (dBc)
LTC2215 SNR and SFDR vs Sample Rate, fIN = 5.2MHz
110 LIMIT 105 100 95 90 85 SNR 80 75 70 SFDR
HD3 SNR (dBFS)
95 HD2 90 85 80 75 70 0 50 100 150 200 INPUT FREQUENCY (MHz) 250
22165 G69
SFDR
79 78 77 76 0 50 100 150 200 INPUT FREQUENCY (MHz) 250
22165 G70
0
40 80 SAMPLE RATE (Msps)
120
22165 G71
LTC2215 SNR and SFDR vs Supply Voltage (VDD), fIN = 5.1MHz
110 LOWER LIMIT 105 SNR (dBFS) AND SFDR (dBc) 100 95 90 85 SNR 80 75 70 2.8 150 125 3.0 3.2 3.4 SUPPLY VOLTAGE (V) 3.6
22165 G72
LTC2215 IVDD vs Sample Rate and Supply Voltage, fIN = 5MHz, -1dBFS
275 250 225
SFDR
UPPER LIMIT
IVDD (mA)
VDD = 3.465V 200 175 VDD = 3.135V
VDD = 3.3V
0
40 80 120 SAMPLE RATE (Msps)
160
22165 G73
LTC2215 SNR and SFDR vs Clock Duty Cycle, fIN = 5.2MHz
110 SFDR DCS ON 100 SNR (dBFS) AND SFDR (dBc) SFDR DCS OFF SFDR (dBc) 110 105 100 95 90 85 80 75 70 65 60 30 40 50 60 DUTY CYCLE (%) 70
22165 G74
LTC2215 SFDR vs Analog Input Common Mode Voltage, 5MHz and 70MHz, -1dBFS
5MHz
90
SNR DCS ON 80 SNR DCS OFF 70
70MHz
60 0.5 0.75 1 1.25 1.5 1.75 2
22165 G75
ANALOG INPUT COMMON MODE VOLTAGE (V)
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LTC2216/LTC2215 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2216/LTC2215 Normalized Full-Scale vs Temperature, Internal Reference, 5 Units
1.005 1.004 NORMALIZED FULL SCALE 1.003 OFFSET VOLTAGE (mV) 1.002 1.001 1 0.999 0.998 0.997 0.996 0.995 -40 -20 0 20 40 60 80
22165 G76
LTC2216/LTC2215 Input Offset Voltage vs Temperature, Internal Reference, 5 Units
5 4 NORMALIZED FULL SCALE 3 2 1 0 -1 -2 -3 -4 -5 -40 -20 0 20 40 60 80
22165 G77
LTC2216/LTC2215 Normalized Full-Scale vs Temperature, External Reference, 5 Units
1.005 1.004 1.003 1.002 1.001 1 0.999 0.998 0.997 0.996 0.995 -40 -20 0 20 40 60 80
22165 G78
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
LTC2216/LTC2215 Input Offset Voltage vs Temperature, External Reference, 5 Units
5 4 FULL-SCALE ERROR (%) 3
OFFSET VOLTAGE (mV)
LTC2216/LTC2215 Mid-Scale Settling After Wake-Up from Shutdown or Starting Encode Clock
0.5 0.4 WAKE-UP FULL-SCALE ERROR (%) 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 CLOCK START 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 300 600 900 1200 1500 TIME AFTER WAKE-UP OR CLOCK START (s)
22165 G80
LTC2216/LTC2215 Full-Scale Settling After Wake-Up from Shutdown or Starting Encode Clock
2 1 0 -1 -2 -3 -4 -5 -40 -20 0 20 40 TEMPERATURE (C) 60 80
22165 G79
WAKE-UP
CLOCK START
0 400 800 1200 1600 2000 TIME AFTER WAKE-UP OR CLOCK START (s)
22165 G81
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LTC2216/LTC2215 PIN FUNCTIONS
For CMOS Mode. Full Rate or Demultiplexed SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full-scale ADC range of 2.75V. GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. VCM (Pin 3): 1.575V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2F Ceramic chip capacitors are recommended. . VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. Bypass to GND with 1F ceramic chip capacitors. AIN+ (Pin 8): Positive Differential Analog Input. AIN- (Pin 9): Negative Differential Analog Input. (Pin 12): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2k resistor. Output data can be latched on the rising edge of ENC+. ENC- (Pin 13): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC -. Internally biased to 1.6V through a 6.2k resistor. Bypass to ground with a 0.1F capacitor for a single-ended Encode signal. SHDN (Pin 19): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin 20): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. DB0-DB15 (Pins 21-30 and 33-38): Digital Outputs, B Bus. DB15 is the MSB. Active in demultiplexed mode. The B bus is in high impedance state in full rate CMOS mode. OGND (Pins 31 and 50): Output Driver Ground. OVDD (Pins 32 and 49): Positive Supply for the Output Drivers. Bypass to ground with 1F capacitor. OFB (Pin 39): Over/Under Flow Digital Output for the B Bus. OFB is high when an over or under flow has occurred on the B bus. At high impedance state in full rate CMOS mode. ENC+ CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the falling edge of CLKOUTB. CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the rising edge of CLKOUTA. DA0-DA15 (Pins 42-48 and 51-59): Digital Outputs, A Bus. DA15 is the MSB. Output bus for full rate CMOS mode and demultiplexed mode. OFA (Pin 60): Over/Under Flow Digital Output for the A Bus. OFA is high when an over or under flow has occurred on the A bus. LVDS (Pin 61): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode. MODE (Pin 62): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2's complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2's complement output format and disables the clock duty cycle stabilizer. RAND (Pin 63): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference. NC (Pin 64): Not Connected Internally. For pin compatibility with the LTC2208 this pin should be connected to GND or VDD as required. Otherwise no connection. GND (Exposed Pad): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground.
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LTC2216/LTC2215 PIN FUNCTIONS
For LVDS Mode. STANDARD or LOW POWER SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full-scale ADC range of 2.75V. GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. VCM (Pin 3): 1.575V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2F Ceramic chip capacitors are recom. mended. VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. Bypass to GND with 1F ceramic chip capacitors. AIN + (Pin 8): Positive Differential Analog Input. AIN - (Pin 9): Negative Differential Analog Input. ENC + (Pin 12): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2k resistor. Output data can be latched on the rising edge of ENC+. ENC - (Pin 13): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC -. Internally biased to 1.6V through a 6.2k resistor. Bypass to ground with a 0.1F capacitor for a single-ended Encode signal. SHDN (Pin 19): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are set in high impedance state. DITH (Pin 20): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of the data sheet for details on dither operation. D0-/D0+ to D15-/D15+ (Pins 21-30, 33-38, 41-48 and 51-58): LVDS Digital Outputs. All LVDS outputs require differential 100 termination resistors at the LVDS receiver. D15+/D15- is the MSB. OGND (Pins 31 and 50): Output Driver Ground. OVDD (Pins 32 and 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1F capacitor. CLKOUT-/CLKOUT + (Pins 39 and 40): LVDS Data Valid 0utput. Latch data on the rising edge of CLKOUT +, falling edge of CLKOUT -. OF-/OF+ (Pins 59 and 60): Over/Under Flow Digital Output OF is high when an over or under flow has occurred. LVDS (Pin 61): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode. MODE (Pin 62): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2's complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2's complement output format and disables the clock duty cycle stabilizer. RAND (Pin 63): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. The mode of operation reduces the effects of digital output interference. NC (Pin 64): Not Connected Internally. For pin compatibility with the LTC2208 this pin should be connected to GND or VDD as required. Otherwise no connection. GND (Exposed Pad Pin 65): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground.
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LTC2216/LTC2215 BLOCK DIAGRAM
AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND VDD
AIN-
DITHER SIGNAL GENERATOR CORRECTION LOGIC AND SHIFT REGISTER
RANGE SELECT SENSE PGA VCM ADC REFERENCE
ADC CLOCKS OVDD CLKOUT+ CLKOUT- OF+ OF- D15+ D15- D0+ D0-
BUFFER VOLTAGE REFERENCE
DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER
CONTROL LOGIC
OUTPUT DRIVERS
* * *
OGND ENC+ ENC- SHDN RAND M0DE LVDS DITH
22165 F01
Figure 1. Functional Block Diagram
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LTC2216/LTC2215 OPERATION
DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency (Nyquist Frequency). Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (Nyquist Frequency). THD is expressed as: THD = - 20Log If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full-scale and expressed in dBFS. Full Power Bandwidth The Full Power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB from a full-scale input signal. Aperture Delay Time The time from when a rising ENC + equals the ENC- voltage to the instant that the input signal is held by the sampleand-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal-to-noise ratio term due to the jitter alone will be: SNRJITTER = -20log (2 * fIN * tJITTER) This formula states SNR due to jitter alone at any amplitude in terms of dBc.
((
V2 2 + V3 2 + V4 2 + ...VN 2 / V1
)
)
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.
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LTC2216/LTC2215 APPLICATIONS INFORMATION
CONVERTER OPERATION The LTC2216/LTC2215 are CMOS pipelined multistep converters with a low noise front-end. As shown in Figure 1, these converters have five pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles later (see the Timing Diagram section). The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. The encode input is also differential for improved common mode noise immunity. The LTC2216/LTC2215 have two phases of operation, determined by the state of the differential ENC+/ENC - input pins. For brevity, the text will refer to ENC+ greater than ENC - as ENC high and ENC+ less than ENC - as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "input S/H" shown in the block diagram. At the instant that ENC transitions from low to high, the voltage on the sample capacitors is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H amplifier during the high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2216/ LTC2215 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the NMOS transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions for high to low, the inputs are reconnected to
LTC2216/LTC2215 VDD RPARASITIC 3 AIN+ VDD RPARASITIC 3 AIN- CPARASITIC 1.8pF VDD CPARASITIC 1.8pF RON 20 CSAMPLE 7.3pF RON 20
CSAMPLE 7.3pF
1.6V 6k ENC+ ENC- 6k 1.6V
22165 F02
Figure 2. Equivalent Input Circuit
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LTC2216/LTC2215 APPLICATIONS INFORMATION
the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing 0.6875V for the 2.75V range, around a common mode voltage of 1.575V. The VCM output pin (Pin 3) is designed to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with 2.2F or greater. Input Drive Impedance As with all high performance, high speed ADCs the dynamic performance of the LTC2216/LTC2215 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC the sample and hold circuit will connect the sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2 * fENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance it is recommended to have a source impedance of 100 or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. INPUT DRIVE CIRCUITS Input Filtering A first-order RC low-pass filter at the input of the ADC can serve two functions: limit the noise from input circuitry and provide isolation from ADC S/H switching. The LTC2216/LTC2215 have a very broadband S/H circuit, DC to 400MHz. This can be used in a wide range of applications, therefore, it is not possible to provide a single recommended RC filter. Figures 3 and 4 show two examples of input RC filtering for two ranges of input frequencies. In general it is desirable to make the capacitors as large as can be tolerated-this will help suppress random noise as well as noise coupled from the digital circuitry. The LTC2216/LTC2215 do not require any input filter to achieve data sheet specifications; however, no filtering will put more stringent noise requirements on the input drive circuitry. Transformer Coupled Circuits Figure 3 shows the LTC2216/LTC2215 being driven by an RF transformer with a center-tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the ADC. Source impedance greater than 50 can reduce the input bandwidth and increase
VCM 5 10 T1 35 0.1F 10 T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2F 35 8.2pF 5 AIN- 8.2pF
22165 F03
2.2F 5 AIN+ 8.2pF LTC2216/ LTC2215
Figure 3. Single-Ended to Differential Conversion Using a Transformer. Recommended for Input Frequencies from 5MHz to 100MHz
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LTC2216/LTC2215 APPLICATIONS INFORMATION
high frequency distortion. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Center-tapped transformers provide a convenient means of DC biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. Figure 4 shows transformer coupling using a transmission line balun transformer. This type of transformer has much better high-frequency response and balance than flux coupled center-tap transformers. Coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.575V.
VCM 5 0.1F ANALOG INPUT T1 1:1 10 25 0.1F 4.7pF 25 10 5 AIN- 4.7pF
22165 F04
VCM HIGH SPEED DIFFERENTIAL AMPLIFIER ANALOG INPUT 2.2F 25 12pF AIN+ LTC2216/ LTC2215
+
CM
+ -
25
-
AIN- 12pF
22165 F05
AMPLIFIER = LTC6600-20, LTC1993, ETC.
Figure 5. DC Coupled Input with Differential Amplifier
Reference Operation Figure 6 shows the LTC2216/LTC2215 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. The LTC2216/LTC2215 has three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in a full-scale range of 2.75VP-P. A 1.575V output, VCM, is provided for a common mode bias for input drive circuitry. An external bypass capacitor is required for the VCM output. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference; which will not be stable without this capacitor. The minimum value required for stability is 2.2F .
RANGE SELECT AND GAIN CONTROL SENSE PGA
2.2F 5 AIN+ 4.7pF LTC2216/ LTC2215
0.1F
T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2F
Figure 4. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 100MHz to 250MHz
Direct Coupled Circuits Figure 5 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally, wideband op amps or differential amplifiers tend to have high noise. As a result, the SNR will be degraded unless the noise bandwidth is limited prior to the ADC input.
TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT AN EXTERNAL 2.5V REFERENCE OR INPUT AN EXTERNAL 1.25V REFERENCE INTERNAL ADC REFERENCE
2.5V BANDGAP REFERENCE VCM 2.2F BUFFER 1.575V
22165 F06
Figure 6. Reference Circuit
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LTC2216/LTC2215 APPLICATIONS INFORMATION
The internal programmable gain amplifier provides the internal reference voltage for the ADC. This amplifier has very stringent settling requirements and therefore is not accessible for external use. The SENSE pin can be driven 5% around the nominal 2.5V or 1.25V external reference inputs. This adjustment range can be used to trim the ADC gain error or other system gain errors. When selecting the internal reference, the SENSE pin should be tied to VDD as close to the converter as possible. If the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1F ceramic capacitor.
VCM 2.2F 2 6 SENSE 2.2F LTC2216/ LTC2215 ENC+ VDD ENC- 1.6V 6k
22165 F07
3. If the ADC is clocked with a fixed-frequency sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to VDD. Each input may be driven from ground to VDD for single-ended drive.
LTC2216/LTC2215 VDD TO INTERNAL ADC CLOCK DRIVERS VDD 1.6V 6k
1.575V
3.3V 1F
LTC1461-2.5 4
Figure 7. A 2.75V Range ADC with an External 2.5V Reference
22165 F08
Driving the Encode Inputs The noise performance of the LTC2216/LTC2215 can depend on the encode signal quality as much as on the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies), take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the amplitude.
Figure 8. Equivalent Encode Input Circuit
0.1F
T1 50
ENC+
100 8.2pF 0.1F 50 0.1F ENC-
LTC2216/ LTC2215
22165 F09
T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE
Figure 9. Balun-Driven Encode
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LTC2216/LTC2215 APPLICATIONS INFORMATION
VTHRESHOLD = 1.6V 1.6V ENC+ ENC- 0.1F
22165 F10
LTC2216/ LTC2215
use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2216/LTC2215 sample rate is determined by droop affecting the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for both the LTC2215 and LTC2216 is 1Msps. DIGITAL OUTPUTS
Figure 10. Single-Ended ENC Drive, Not Recommended for Low Jitter
3.3V MC100LVELT22 3.3V 130 Q0 130 ENC+ LTC2216/ LTC2215
D0 ENC- Q0 83 83
Digital Output Modes The LTC2216/LTC2215 can operate in four digital output modes: standard LVDS, low power LVDS, full rate CMOS, and demultiplexed CMOS. The LVDS pin selects the mode of operation. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be used to set the 1/3VDD and 2/3VDD logic levels. Table 1 shows the logic states for the LVDS pin.
Table 1. LVDS Pin Function
LVDS 0V(GND) 1/3VDD 2/3VDD VDD DIGITAL OUTPUT MODE Full-Rate CMOS Demultiplexed CMOS Low Power LVDS LVDS
22165 F11
Figure 11. ENC Drive Using a CMOS to PECL Translator
Maximum and Minimum Encode Rates The maximum encode rate for the LTC2216 is 80Msps, while the maximum encode rate for the LTC2215 is 65Msps. For the ADCs to operate properly the encode signal should have a 50% (5%) duty cycle. Each half cycle must have at least 5.94ns for the LTC2216 internal circuitry to have enough settling time for proper operation. For the LTC2215, each half cycle must be at least 7.31ns. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended ENCODE signal asymmetric rise and fall times can result in duty cycles that are far from 50%. An optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. This circuit uses the rising edge of ENC pin to sample the analog input. The falling edge of ENC is ignored and an internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To
Digital Output Buffers (CMOS Modes)
Figure 11 shows an equivalent circuit for a single output buffer in CMOS Mode, Full-Rate or Demultiplexed. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50 to external circuitry and eliminates the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2216/LTC2215 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as the
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LTC2216/LTC2215 APPLICATIONS INFORMATION
ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF A resistor in . series with the output may be used, but is not required since the ADC has a series resistor of 43 on-chip. Lower OVDD voltages will also help reduce interference from the digital outputs.
LTC2216/LTC2215 VDD VDD OVDD 0.5V TO 3.6V 0.1F OVDD DATA FROM LATCH PREDRIVER LOGIC 43 TYPICAL DATA OUTPUT OGND
22165 F12
resistor, even if the signal is not used (such as OF+/OF- or CLKOUT+/CLKOUT-). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length. In Low Power LVDS Mode 1.75mA is steered between the differential outputs, resulting in 175mV at the LVDS receiver's 100 termination resistor. The output common mode voltage is 1.20V, the same as standard LVDS Mode. Data Format The LTC2216/LTC2215 parallel digital output can be selected for offset binary or 2's complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be user to set the 1/3VDD and 2/3VDD logic levels. Table 2 shows the logic states for the MODE pin.
Table 2. MODE Pin Function
MODE 0V(GND) 1/3VDD 2/3VDD VDD OUTPUT FORMAT Offset Binary Offset Binary 2's Complement 2's Complement CLOCK DUTY CYCLE STABILIZER Off On On Off
Figure 12. Equivalent Circuit for a Digital Output Buffer
Digital Output Buffers (LVDS Modes) Figure 13 shows an equivalent circuit for an LVDS output pair. A 3.5mA current is steered from OUT+ to OUT- or vice versa, which creates a 350mV differential voltage across the 100 termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.20V. For proper operation each LVDS output pair must be terminated with an external 100 termination
LTC2216/LTC2215
3.5mA VDD VDD OVDD 43 DATA FROM LATCH PREDRIVER LOGIC 10k 10k OVDD 43 100
OVDD 3.3V 0.1F
LVDS RECEIVER
1.20V
+ -
22165 F13
OGND
Figure 13. Equivalent Output Buffer in LVDS Mode
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LTC2216/LTC2215 APPLICATIONS INFORMATION
Overflow Bit An overflow output bit (OF) indicates when the converter is over-ranged or under-ranged. In CMOS mode, a logic high on the OFA pin indicates an overflow or underflow on the A data bus, while a logic high on the OFB pin indicates an overflow on the B data bus. In LVDS mode, a differential logic high on OF+/OF- pins indicates an overflow or underflow. Output Clock The ADC has a delayed version of the encode input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. In both CMOS modes, A bus data will be updated as CLKOUTA falls and CLKOUTB rises. In demultiplexed CMOS mode the B bus data will be updated as CLKOUTA falls and CLKOUTB rises. In Full Rate CMOS Mode, only the A data bus is active; data may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. In demultiplexed CMOS mode CLKOUTA and CLKOUTB will toggle at 1/2 the frequency of the encode signal. Both the A bus and the B bus may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling, or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. The digital output is "Randomized" by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT output are not affected. The output Randomizer function is active when the RAND pin is high.
LTC2216/LTC2215 CLKOUT CLKOUT
OF
OF
D15
D15 D0
D14
D14 D0
D2
* * *
D2 D0
D1
D1 D0
RAND = HIGH, SCRAMBLE ENABLED
RAND
D0
22165 F14
D0
Figure 14. Functional Equivalent of Digital Output Randomizer
Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. In CMOS mode OVDD can be powered with any logic voltage up to the 3.6V. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. In LVDS Mode, OVDD should be connected to a 3.3V supply and OGND should be connected to GND.
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LTC2216/LTC2215 APPLICATIONS INFORMATION
PC BOARD FPGA CLKOUT
Internal Dither The LTC2216/LTC2215 is a 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels. As shown in Figure 16, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in typically less than 0.5dB elevation in the noise floor of the ADC, as compared to the noise floor with dither off when a suitable input termination is provided (see Demo Board schematic DC996B).
22165 F15
OF
D15 D0 D15 D14 D0 D14 LTC2216/ LTC2215 D2 D0
* * *
D2
D1 D0 D1
D0
D0
Figure 15. Descrambling a Scrambled Digital Output
LTC2216/LTC2215 CLKOUT OF D15 * * * D0
AIN+ ANALOG INPUT AIN- S/H AMP
16-BIT PIPELINED ADC CORE
DIGITAL SUMMATION
OUTPUT DRIVERS
CLOCK/DUTY CYCLE CONTROL
PRECISION DAC
MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR
22165 F16
ENC +
ENC -
DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF
Figure 16. Functional Equivalent Block Diagram of Internal Dither Circuit
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LTC2216/LTC2215 APPLICATIONS INFORMATION
Grounding and Bypassing The LTC2216/LTC2215 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2216/LTC2215 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, and OVDD pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2216/LTC2215 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2216/LTC2215 is transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. It is critical that the exposed pad and all ground pins are connected to a ground plane of sufficient area with as many vias as possible.
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LTC2216/LTC2215 APPLICATIONS INFORMATION
Layer 1 Component Side
Layer 2 GND Plane
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31
LTC2216/LTC2215 APPLICATIONS INFORMATION
Layer 3 GND
Layer 4 GND
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32
LTC2216/LTC2215 APPLICATIONS INFORMATION
Layer 5 GND
Layer 6 Bottom Side
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33
3 VC1 VC2 VC3 VC4 VC5 EN12 EN34 EN58 EN78 EN I1N I1P I2N I2P I3N I3P I4N I4P I5N I5P I6N I6P I7N I7P I8N I8P VE1 VE2 VE3 VE4 VE5 O8N O8P 29 28 O7N O7P 31 30 O6N O6P 33 32 O5N O5P 35 34 O4N O4P 39 38 O3N U3 FIN1108 O3P 41 40 O2N O2P 43 42 O1N O1P 5 44 5 GND R3 DNP R16 100 R17 100 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 R18 100 R19 100 R20 100 R21 100 3 22 27 46 13 OFF 6 VDD ON 4
R45 86.6 R28 10 R11 33.2 C8 4.7pF R27 10 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
R9 10
VCC C26 0.1F C25 0.1F C16 0.1F C18 OPT C19 OPT R37 100 12 25 26 47 48 D13+ D13- D12+ D12- R22 100 D11+ D11- D10+ D10- D9+ D9- 1 2 23 36 37 D8+ D8- CLKCOUT+ CLKOUT- D7- D8+ D8- D5+ D5- R31 100 65 4 5 6 7 8 9 10 11 R35 100 R38 100 R39 100 R40 100 14 15 16 17 18 19 20 21 I1N I1P I2N I2P I3N I3P I4N I4P I5N I5P I6N I6P I7N I7P I8N I8P R32 100 R33 100 R6 1000 R34 100 2 J2 MODE 33 34 35 VC1 VC2 VC3 VC4 VC5 36 37 12 25 26 47 48 D7+ 38 39 3.3V 40 41 U2 LTC2216IUP/LTC2215IUP 42 43 44 45 46 R30 100 47 48 R23 100 OVDD49 J4
R36 R44 86.6 86.6 R12 33.2 R10 10 NC OF+ OF- D15+ D15- D14+ RAND MODE LVDS D14-
C8 8.2pF 1 SENSE GND2 VCM GND VDD5 VDD6 GND7 AINP AINN GND10 GND11 ENCP ENCN GND14 VDD15 VDD16 VDD17 GND18 SHDN DITH D0- D0+ D1- D1+ D2- D2+ D3- D3+ D4- D4+ OGND31 OVDD32 R15 5 3 C13 2.2F 4 5 6 C17 2.2F R14 1000 8 9 R13 100 11 12 13 14 15 16 J3 1 3 17 18 19 20 21 22 23 24 25 26 27 27 29 30 31 32 5 RUN OFF 6 SHDN ON 4 VCC DITHER 2 10 7 2 OGND50
LTC2216/LTC2215
C10 8.2pF
**
APPLICATIONS INFORMATION
VE1 VE2 VE3 VE4 VE5
C20 0.1F C22 0.1F T2 INPUT FREQUENCY 1MHz TO 70MHz 70MHz TO 140MHz 1MHz TO 70MHz 2 WBC1-1LB 70MHz TO 140MHz 3 4 GND DOUT- 5 EN DOUT+ 6 1MHz TO 70MHz 70MHz TO 140MHz C15 0.1F GND VCC 7 RIN- RIN+ 1 8 U5 FIN1101K8X R41 100
3.3V
1 2 23 36 37
34
3.3V 1 2 MEC8-150-02-L-D-EDGE_CONNRE-DIM J1E J1O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 3 22 27 46 13 EN12 EN34 EN58 EN78 EN O1N O1P O2N O2P U4 O3N FIN1108 O3P O4N O4P O5N O5P O6N O6P O7N O7P O8N O8P 45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 R24 100k 3.3V R29 4990 1 3 VDD GND R8 1000 6 4 R7 1000 5 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 C27 0.1F R25 4990 R43 FERRITE BEAD 8 VCC C14 4.7F C24 4.7F C38 4.7F ARRAY EEPROM U1 24LC02ST R42 FERRITE BEAD 6 6CL 6DA WP A2 GND 4 A1 A0 5 7 3 2 1 R26 4990 WBC1-1LB WBC1-1LB C34 0.1F C35 0.1F C36 0.1F C28 0.1F C29 0.1F C30 0.1F C31 0.1F C32 0.1F
22165 F17
J5 AIN
C6 0.01F
L1 56nH
T1 MABA-007159- T2 000000 **
C7 0.01F
C5 0.01F
C12 0.1F
TP1 EXT REF
J7 ENCODE C2 T3 CLOCK 0.01F ETC1-1-13
R5 5.1
**
R2 49.9
C1 0.01F
C3 0.01F
R1 49.9
C4 8.2pF R4 5.1
VCC
VCC
TP5 3.3V
1
2
3
4
TP2 PWR GND
5
J9 AUX PWR CONNECTOR
6
* VERSION TABLE
ASSEMBLY
U2
BITS
C8
C9-10
L1
R36, 44
R45
DC996B-E
LTC2217IUP
16
4.7pF
8.2pF
56nH
86.6
86.6
MABAES0060
DC996B-F
LTC2217IUP
16
1.8pF
3.9pF
18nH
43.2
182
DC996B-G
LTC2216IUP
16
4.7pF
8.2pF
56nH
86.6
86.6
MABAES0060
DC996B-H
LTC2216IUP
16
1.8pF
3.9pF
18nH
43.2
182
DC996B-I
LTC2215IUP
16
4.7pF
8.2pF
56nH
86.6
86.6
MABAES0060
DC996B-J
LTC2215IUP
16
4.7pF
7.9pF
18nH
43.2
182
22165f
LTC2216/LTC2215 PACKAGE DESCRIPTION
UP Package 64-Lead Plastic QFN (9mm x 9mm)
(Reference LTC DWG # 05-08-1705)
0.70 0.05
7.15 0.05
7.50 REF 8.10 0.05 9.50 0.05 (4 SIDES)
7.15 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 9 .00 0.10 (4 SIDES) 0.75 0.05 R = 0.115 TYP
R = 0.10 TYP
63 64 0.40 0.10 1 2 PIN 1 CHAMFER C = 0.35
PIN 1 TOP MARK (SEE NOTE 5)
7.15 0.10 7.50 REF (4-SIDES)
7.15 0.10
(UP64) QFN 0406 REV C
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
22165f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC2216/LTC2215 RELATED PARTS
PART NUMBER LT1993 LTC2202 LTC2203 LTC2204 LTC2205 LTC2206 LTC2207 LTC2208 LTC2209 LTC2217 LTC2220 LTC2220-1 LTC2249 LTC2250 LTC2251 LTC2252 LTC2253 LTC2254 LTC2255 LTC2299 LT5522 LT5527 LT5557 DESCRIPTION High Speed Differential Op Amp 16-Bit, 10Msps ADC 16-Bit, 25Msps ADC 16-Bit, 40Msps ADC 16-Bit, 65Msps ADC 16-Bit, 80Msps ADC 16-Bit, 105Msps ADC 16-Bit, 130Msps ADC 16-Bit, 160Msps ADC 16-Bit, 105Msps ADC 12-Bit, 170Msps ADC 12-Bit, 185Msps ADC 14-Bit, 65Msps ADC 10-Bit, 105Msps ADC 10-Bit, 125Msps ADC 12-Bit, 105Msps ADC 12-Bit, 125Msps ADC 14-Bit, 105Msps ADC 14-Bit, 125Msps ADC Dual 14-Bit, 80Msps ADC 400MHz to 2.7GHz High Linearity Downconverting Mixer 400MHz to 3.7GHz High Linearity Downconverting Mixer COMMENTS 600MHz BW, 75dBc Distortion at 70MHz 150mW, 81.6dB SNR, 100dB SFDR 230mW, 81.6dB SNR, 100dB SFDR 470mW, 79.1dB SNR, 100dB SFDR 530mW, 79dB SNR, 100dB SFDR 725mW, 77.9dB SNR, 100dB SFDR 900mW, 77.9dB SNR, 100dB SFDR 1250mW, 77.7dB SNR, 100dB SFDR 1450mW, 77.1dB SNR, 100dB SFDR Low Noise 1190mW, 81.2dB SNR, 100dB SFDR 890mW, 67.5dB SNR, 9mm x 9mm QFN Package 910mW, 67.5dB SNR, 9mm x 9mm QFN Package 230mW, 73dB SNR, 5mm x 5mm QFN Package 320mW, 61.6dB SNR, 5mm x 5mm QFN Package 395mW, 61.6dB SNR, 5mm x 5mm QFN Package 320mW, 70.2dB SNR, 5mm x 5mm QFN Package 395mW, 70.2dB SNR, 5mm x 5mm QFN Package 320mW, 72.5dB SNR, 5mm x 5mm QFN Package 395mW, 72.4dB SNR, 5mm x 5mm QFN Package 445mW, 73dB SNR, 9mm x 9mm QFN Package 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports High IIP3: 23.5dBm at 1.9GHz, Conversion Gain: 2.3dB at 1.9GHz, NF = 12.5dB
400MHz to 3.7GHz High Signal Level High IIP3: 23.5dBm at 3.5GHz, Conversion Gain: 1.7dB at 3.5GHz Downconverting Mixer
22165f
36 Linear Technology Corporation
(408) 432-1900
LT 0208 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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